Method and system for a configurable tuned MOS capacitor

ABSTRACT

Methods and systems for a configurable tuned MOS capacitor are disclosed and may include filtering undesired signals in a chip utilizing one or more configurable MOS capacitors comprising one or more MOS transistors. The source and drain terminals of the MOS transistors may be coupled together. The filtering frequencies may be tuned by configuring a resonance frequency of a matching circuit coupled to the source and drain terminals. The matching circuit may include a variable capacitor, which may include an array of binary-weighted addressable capacitors. The addressable capacitors may include MOS transistors. The matching circuit may include a variable inductor such as a multi-tap transmission line, and may be integrated on the chip and/or on a package to which the chip is bonded. A capacitance value of the configurable MOS capacitor may be configured utilizing a bias voltage on the matching circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

[Not Applicable]

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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MICROFICHE/COPYRIGHT REFERENCE

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FIELD OF THE INVENTION

Certain embodiments of the invention relate to wireless communication. More specifically, certain embodiments of the invention relate to a method and system for a configurable tuned MOS capacitor.

BACKGROUND OF THE INVENTION

Mobile communications have changed the way people communicate and mobile phones have been transformed from a luxury item to an essential part of every day life. The use of mobile phones is today dictated by social situations, rather than hampered by location or technology. While voice connections fulfill the basic need to communicate, and mobile voice connections continue to filter even further into the fabric of every day life, the mobile Internet is the next step in the mobile communication revolution. The mobile Internet is poised to become a common source of everyday information, and easy, versatile mobile access to this data will be taken for granted.

As the number of electronic devices enabled for wireline and/or mobile communications continues to increase, significant efforts exist with regard to making such devices more power efficient. For example, a large percentage of communications devices are mobile wireless devices and thus often operate on battery power. Additionally, transmit and/or receive circuitry within such mobile wireless devices often account for a significant portion of the power consumed within these devices. Moreover, in some conventional communication systems, transmitters and/or receivers are often power inefficient in comparison to other blocks of the portable communication devices. Accordingly, these transmitters and/or receivers have a significant impact on battery life for these mobile wireless devices.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method for a configurable tuned MOS capacitor, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

Various advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram of an exemplary wireless system, which may be utilized in accordance with an embodiment of the invention.

FIG. 2 is a block diagram illustrating an exemplary MOS capacitor and matching circuit, in accordance with an embodiment of the invention.

FIG. 3 is a diagram showing a top view of an exemplary matching circuit module with a multi-tap transmission line on a chip, in accordance with an embodiment of the invention.

FIG. 4 is a diagram illustrating a cross sectional view of a multi-layer package with an integrated transmission line, in accordance with an embodiment of the invention.

FIG. 5 is a block diagram illustrating exemplary steps for utilizing a variable MOS capacitor, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain aspects of the invention may be found in a method and system for a configurable tuned MOS capacitor. Exemplary aspects of the invention may comprise, in a chip comprising one or more transmitters and one or more receivers, filtering undesired signals utilizing one or more configurable MOS capacitors comprising one or more MOS transistors. The source and drain terminals of the MOS transistors may be coupled together. The filtering frequencies may be tuned by configuring a resonance frequency of a matching circuit coupled to the source and drain terminals. The matching circuit may comprise a variable capacitor, which may comprise an array of binary-weighted addressable capacitors. The addressable capacitors may comprise MOS transistors. The matching circuit may comprise a variable inductor such as a multi-tap transmission line, and may be integrated on the chip and/or on a package to which the chip is bonded. A capacitance value of the configurable MOS capacitor may be configured utilizing a bias voltage on the matching circuit.

FIG. 1 is a block diagram of an exemplary wireless system, which may be utilized in accordance with an embodiment of the invention. Referring to FIG. 1, the wireless device 150 may comprise an antenna 151, a transceiver 152, a baseband processor 154, a processor 156, a system memory 158, a logic block 160, a chip 162, MOS capacitors 164, a matching circuit module 165, an external headset port 166, and a package 167. The wireless device 150 may also comprise an analog microphone 168, integrated hands-free (IHF) stereo speakers 170, a hearing aid compatible (HAC) coil 174, a dual digital microphone 176, a vibration transducer 178, a keypad and/or touchscreen 180, and a display 182.

The transceiver 152 may comprise suitable logic, circuitry, interfaces, and/or code that may be enabled to modulate and upconvert baseband signals to RF signals for transmission by one or more antennas, which may be represented generically by the antenna 151. The transceiver 152 may also be enabled to downconvert and demodulate received RF signals to baseband signals. The RF signals may be received by one or more antennas, which may be represented generically by the antenna 151. Different wireless systems may use different antennas for transmission and reception. The transceiver 152 may be enabled to execute other functions, for example, filtering the baseband and/or RF signals, and/or amplifying the baseband and/or RF signals. Although a single transceiver 152 is shown, the invention is not so limited. Accordingly, the transceiver 152 may be implemented as a separate transmitter and a separate receiver. In addition, there may be a plurality of transceivers, transmitters and/or receivers. In this regard, the plurality of transceivers, transmitters and/or receivers may enable the wireless device 150 to handle a plurality of wireless protocols and/or standards including cellular, WLAN and PAN. Wireless technologies handled by the wireless device 150 may comprise GSM, CDMA, CDMA2000, WCDMA, GMS, GPRS, EDGE, WIMAX, WLAN, LTE, 3GPP, UMTS, BLUETOOTH, and ZIGBEE, for example.

The baseband processor 154 may comprise suitable logic, circuitry, interfaces, and/or code that may be enabled to process baseband signals for transmission via the transceiver 152 and/or the baseband signals received from the transceiver 152. The processor 156 may be any suitable processor or controller such as a CPU, DSP, ARM, or any type of integrated circuit processor. The processor 156 may comprise suitable logic, circuitry, and/or code that may be enabled to control the operations of the transceiver 152 and/or the baseband processor 154. For example, the processor 156 may be utilized to update and/or modify programmable parameters and/or values in a plurality of components, devices, and/or processing elements in the transceiver 152 and/or the baseband processor 154. At least a portion of the programmable parameters may be stored in the system memory 158.

Control and/or data information, which may comprise the programmable parameters, may be transferred from other portions of the wireless device 150, not shown in FIG. 1, to the processor 156. Similarly, the processor 156 may be enabled to transfer control and/or data information, which may include the programmable parameters, to other portions of the wireless device 150, not shown in FIG. 1, which may be part of the wireless device 150.

The processor 156 may utilize the received control and/or data information, which may comprise the programmable parameters, to determine an operating mode of the transceiver 152. For example, the processor 156 may be utilized to select a specific frequency for a local oscillator, a specific gain for a variable gain amplifier, configure the local oscillator and/or configure the variable gain amplifier for operation in accordance with various embodiments of the invention. Moreover, the specific frequency selected and/or parameters needed to calculate the specific frequency, and/or the specific gain value and/or the parameters, which may be utilized to calculate the specific gain, may be stored in the system memory 158 via the processor 156, for example. The information stored in system memory 158 may be transferred to the transceiver 152 from the system memory 158 via the processor 156.

The system memory 158 may comprise suitable logic, circuitry, interfaces, and/or code that may be enabled to store a plurality of control and/or data information, including parameters needed to calculate frequencies and/or gain, and/or the frequency value and/or gain value. The system memory 158 may store at least a portion of the programmable parameters that may be manipulated by the processor 156.

The logic block 160 may comprise suitable logic, circuitry, interfaces, and/or code that may enable controlling of various functionalities of the wireless device 150. For example, the logic block 160 may comprise one or more state machines that may generate signals to control the transceiver 152 and/or the baseband processor 154. The logic block 160 may also comprise registers that may hold data for controlling, for example, the transceiver 152 and/or the baseband processor 154. The logic block 160 may also generate and/or store status information that may be read by, for example, the processor 156. Amplifier gains and/or filtering characteristics, for example, may be controlled by the logic block 160.

The BT radio/processor 163 may comprise suitable circuitry, logic, interfaces, and/or code that may enable transmission and reception of Bluetooth signals. The BT radio/processor 163 may enable processing and/or handling of BT baseband signals. In this regard, the BT radio/processor 163 may process or handle BT signals received and/or BT signals transmitted via a wireless communication medium. The BT radio/processor 163 may also provide control and/or feedback information to/from the baseband processor 154 and/or the processor 156, based on information from the processed BT signals. The BT radio/processor 163 may communicate information and/or data from the processed BT signals to the processor 156 and/or to the system memory 158. Moreover, the BT radio/processor 163 may receive information from the processor 156 and/or the system memory 158, which may be processed and transmitted via the wireless communication medium a Bluetooth headset, for example.

The CODEC 172 may comprise suitable circuitry, logic, interfaces, and/or code that may process audio signals received from and/or communicated to input/output devices. The input devices may be within or communicatively coupled to the wireless device 150, and may comprise the analog microphone 168, the stereo speakers 170, the hearing aid compatible (HAC) coil 174, the dual digital microphone 176, and the vibration transducer 178, for example. The CODEC 172 may be operable to up-convert and/or down-convert signal frequencies to desired frequencies for processing and/or transmission via an output device. The CODEC 172 may enable utilizing a plurality of digital audio inputs, such as 16 or 18-bit inputs, for example. The CODEC 172 may also enable utilizing a plurality of data sampling rate inputs. For example, the CODEC 172 may accept digital audio signals at sampling rates such as 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and/or 48 kHz. The CODEC 172 may also support mixing of a plurality of audio sources. For example, the CODEC 172 may support audio sources such as general audio, polyphonic ringer, I²S FM audio, vibration driving signals, and voice. In this regard, the general audio and polyphonic ringer sources may support the plurality of sampling rates that the audio CODEC 172 is enabled to accept, while the voice source may support a portion of the plurality of sampling rates, such as 8 kHz and 16 kHz, for example.

The CODEC 172 may utilize a programmable infinite impulse response (IIR) filter and/or a programmable finite impulse response (FIR) filter for at least a portion of the audio sources to compensate for passband amplitude and phase fluctuation for different output devices. In this regard, filter coefficients may be configured or programmed dynamically based on current operations. Moreover, the filter coefficients may be switched in one-shot or may be switched sequentially, for example. The CODEC 172 may also utilize a modulator, such as a Delta-Sigma (Δ-Σ) modulator, for example, to code digital output signals for analog processing.

The chip 162 may comprise an integrated circuit with multiple functional blocks integrated within, such as the transceiver 152, the processor 156, the baseband processor 154, the BT radio/processor 163, the MOS capacitors 164, the matching circuit module 165, and the CODEC 172. The number of functional blocks integrated in the chip 162 is not limited to the number shown in FIG. 1. Accordingly, any number of blocks may be integrated on the chip 162 depending on chip space and wireless device 150 requirements, for example.

The MOS capacitors 164 may comprise a plurality of CMOS transistor pairs with source and drain terminals coupled together and also to a bias voltage through the matching circuit module 165. The CMOS transistor pairs may comprise n-channel and/or p-channel transistors, for example.

The matching circuit module 165 may comprise suitable circuitry, logic, interfaces, and/or code that may be operable to provide a frequency-dependent impedance between the MOS capacitors 164 and a bias voltage. Accordingly, the matching circuit module 165 may comprise a parallel LC circuit comprising configurable capacitors and inductors, as described with respect to FIG. 2. For example, the variable inductance may comprise a plurality of discrete inductors and/or a multi-tap transmission-line inductor, and the variable capacitors may comprise an array of individually addressable capacitors.

The external headset port 166 may comprise a physical connection for an external headset to be communicatively coupled to the wireless device 150. The analog microphone 168 may comprise suitable circuitry, logic, and/or code that may detect sound waves and convert them to electrical signals via a piezoelectric effect, for example. The electrical signals generated by the analog microphone 168 may comprise analog signals that may require analog to digital conversion before processing.

The package 167 may comprise a printed circuit board or other support structure for the chip 162 and other components of the wireless device 150. The package 167 may comprise an insulating material, for example, and may provide isolation between electrical components mounted on the package 167.

The stereo speakers 170 may comprise a pair of speakers that may be operable to generate audio signals from electrical signals received from the CODEC 172. The HAC coil 174 may comprise suitable circuitry, logic, and/or code that may enable communication between the wireless device 150 and a T-coil in a hearing aid, for example. In this manner, electrical audio signals may be communicated to a user that utilizes a hearing aid, without the need for generating sound signals via a speaker, such as the stereo speakers 170, and converting the generated sound signals back to electrical signals in a hearing aid, and subsequently back into amplified sound signals in the user's ear, for example.

The dual digital microphone 176 may comprise suitable circuitry, logic, and/or code that may be operable to detect sound waves and convert them to electrical signals. The electrical signals generated by the dual digital microphone 176 may comprise digital signals, and thus may not require analog to digital conversion prior to digital processing in the CODEC 172. The dual digital microphone 176 may enable beamforming capabilities, for example.

The vibration transducer 178 may comprise suitable circuitry, logic, and/or code that may enable notification of an incoming call, alerts and/or message to the wireless device 150 without the use of sound. The vibration transducer may generate vibrations that may be in synch with, for example, audio signals such as speech or music.

In operation, control and/or data information, which may comprise the programmable parameters, may be transferred from other portions of the wireless device 150, not shown in FIG. 1, to the processor 156. Similarly, the processor 156 may be enabled to transfer control and/or data information, which may include the programmable parameters, to other portions of the wireless device 150, not shown in FIG. 1, which may be part of the wireless device 150.

The processor 156 may utilize the received control and/or data information, which may comprise the programmable parameters, to determine an operating mode of the transceiver 152. For example, the processor 156 may be utilized to select a specific frequency for a local oscillator, a specific gain for a variable gain amplifier, configure the local oscillator and/or configure the variable gain amplifier for operation in accordance with various embodiments of the invention. Moreover, the specific frequency selected and/or parameters needed to calculate the specific frequency, and/or the specific gain value and/or the parameters, which may be utilized to calculate the specific gain, may be stored in the system memory 158 via the processor 156, for example. The information stored in system memory 158 may be transferred to the transceiver 152 from the system memory 158 via the processor 156.

The CODEC 172 in the wireless device 150 may communicate with the processor 156 in order to transfer audio data and control signals. Control registers for the CODEC 172 may reside within the processor 156. The processor 156 may exchange audio signals and control information via the system memory 158. The CODEC 172 may up-convert and/or down-convert the frequencies of multiple audio sources for processing at a desired sampling rate.

The signals processed by the processor 156 and/or the baseband processor 154 may be communicated to and/or from devices that may distort the desired signals or receive noise signals, for example. Accordingly, the MOS capacitors 164, the matching circuit module 165 may be utilized to filter out undesired signals.

In instances where the frequency of an input signal to the gates of the CMOS transistor pairs comprising the MOS capacitors 164 is at a resonant frequency of the matching circuit module 165, each MOS capacitor pair of the MOS capacitors 164 may act as a tunable capacitor between the gate terminals of the CMOS transistor pairs. The capacitance value may be configured by adjusting a bias voltage at the coupled source and drain terminals, thereby adjusting the bias condition of the CMOS transistors.

In instances where a frequency of an input signal to the gates of the CMOS transistor pairs comprising the MOS capacitors 164 is not at a resonant frequency of the matching circuit module 165, each MOS capacitor pair of the MOS capacitors 164 may act as a shunt capacitance to ground, effectively filtering out signals not at the desired resonant frequency.

FIG. 2 is a block diagram illustrating an exemplary MOS capacitor and matching circuit, in accordance with an embodiment of the invention. Referring to FIG. 2, there is shown a MOS capacitor and matching circuit 200 comprising MOS transistors 201A and 201B, and the matching circuit module 165 comprising a variable capacitance 203 and a variable inductance 205. There is also shown input terminals In+ 207 and In− 209, a bias voltage terminal V_(B), and an output terminal 211.

The MOS transistors 201A and 201B are shown as NMOS transistors, but the invention is not so limited. Accordingly, the MOS transistors 201A and 201B may comprise PMOS transistors, for example. The source and drain terminals of the MOS transistors 201A and 201B may be coupled together as well as to one terminal of the matching circuit module 165, thereby defining the output terminal 211. The number of MOS transistors is not limited to the number shown in FIG. 2. Accordingly, any number of MOS transistors may be utilized as variable MOS capacitors, depending on filtering requirements and available chip area.

The variable inductance 205 may comprise a plurality of inductors or may comprise a variable transmission line, for example, that may be operable to provide a plurality of inductance values for the matching circuit module 165. Similarly, the variable capacitance 203 may comprise a plurality of discrete capacitors, such as an array of MOS transistors, for example, or may comprise a single capacitor whose capacitance may be configured, such as by a bias voltage, for example. The capacitance values of the array of capacitors may be binary-weighted, where the capacitance value of a particular capacitor may be one half and double that of adjacent capacitors. Both the variable capacitance 203 and the variable inductance 205 may be integrated on the chip 162.

In operation, an input signal may be communicated to the MOS transistors 201A and 201B at the input terminals In+ 207 and In− 209. The parallel combination of the variable capacitance 203 and the variable inductance 205 may enable the configuration of a variable resonance frequency. In instances where the frequency of the input signal at the input terminals In+ 207 and In− 209 is at a resonant frequency of the matching circuit module 165, the MOS transistors 201A and 201B may act as a tunable capacitor between the input terminals In+ 207 and In− 209. The capacitance between the input terminals In+ 207 and In− 209 may be configured by adjusting the bias voltage V_(B), thereby resulting in adjustment of the bias condition of the MOS transistors 201A and 201B.

In instances where a frequency of an input signal at the input terminals In+ 207 and In− 209 is not at a resonant frequency of the matching circuit module 165, the MOS transistors 201A and 201B may act as a shunt capacitance to ground via the non-resonant state matching circuit module 165, effectively filtering out signals not at the desired resonant frequency. In this manner, a tunable high-frequency filter may be enabled utilizing components integrated on the chip 162.

FIG. 3 is a diagram showing a top view of an exemplary matching circuit module with a multi-tap transmission line on a chip, in accordance with an embodiment of the invention. Referring to FIG. 3, there is shown the chip 162 comprising the matching circuit module 165, baseband/RF circuitry 301, the variable capacitance 203, and the multi-tap transmission line (T-Line) 303.

The baseband/RF circuitry 301 may comprise suitable, circuitry, interfaces, logic, and/or code that may be operable to process baseband and RF signals. Baseband signals may be down-converted received RF signals, or may be generated by input devices such as microphones, for example. The baseband/RF circuitry 301 may comprise the transceiver 152, the baseband processor 154, the processor 156, the CODEC 172, the MOS transistors 201A and 201B, and the BT radio/processor 163, for example, described with respect to FIG. 1.

The multi-tap T-Line 303 may comprise a microstrip and/or coplanar waveguide transmission line, for example, integrated in and/or on the chip 162 that may comprise a plurality of ports, the T-Line ports 305A-305P, such that a configurable inductance may be enabled by coupling to appropriate ports on the T-Line 303.

The T-Line ports 305A-305P may comprise electrical contacts along the length of the multi-tap T-Line 303 that may enable coupling to the T-Line 303 at a plurality of points. In this manner, a configurable inductance may be coupled to the variable capacitance 203 for the matching circuit module 165. The T-Line ports 305A-305P may comprise metal strips, for example, that may be electrically coupled to the multi-tap T-Line 303.

The matching circuit module 165 may be as described with respect to FIGS. 1 and 2, and may also comprise switching capability, such as CMOS switches, for example, to couple the variable capacitance 203 to appropriate ports of the multi-tap T-Line 303. The particular ports of the T-Line ports 305A-305P may be coupled to the variable capacitance 203 depending on the desired inductance to configure the resonance frequency of the matching circuit module 165. In another embodiment of the invention, one or more components of the matching circuit module 165 may be located external to the chip 162. The number of taps 305A-305P is not limited to the number shown in FIG. 3. Accordingly, any number of ports and/or inductance values may be utilized depending on the desired filtering characteristics, for example.

In operation, RF and/or baseband signals may be processed by the baseband/RF circuitry 301. The signal processing may comprise the filtering of undesired signals from received signals, which may be enabled by configurable MOS capacitors, such as the MOS capacitors 164, 201A, and 201B and the matching circuit module 165.

One or more input signals from the baseband/RF circuitry 301 may be communicated to MOS transistors, such as the MOS transistors 201A and 201B described with respect to FIG. 2, which may be communicatively coupled to the matching circuitry 165. In instances where the frequency of the input signal is at a resonant frequency of the matching circuit module 165, the MOS transistors 201A and 201B may act as a tunable capacitor. The resulting capacitance value may be configured by adjusting a bias voltage, such as the bias voltage V_(B), as described with respect to FIG. 2, thereby adjusting the bias condition of the MOS transistors 201A and 201B.

In instances where a frequency of an input signal generated by the baseband/RF circuitry 301 is not at a resonant frequency of the matching circuit module 165, the MOS transistors 201A and 201B may act as a shunt capacitance to ground via the non-resonant state matching circuit module 165, effectively filtering out signals not at the desired resonant frequency. In this manner, a tunable high-frequency filter may be enabled utilizing components integrated on the chip 162. In this manner, the wireless system 150 may communicate higher quality signals due to the filtered signals generated by the configurable MOS capacitors 164, 201A, and 201B.

FIG. 4 is a diagram illustrating a cross sectional view of a multi-layer package with an integrated transmission line, in accordance with an embodiment of the invention. Referring to FIG. 4, there is shown a hybrid circuit 400 comprising a package 167, the multi-tap T-Line 303, and the chip 162, which may comprise a single substrate. The package 167 may comprise insulating material and the vias 410A, and 410B. Additionally, in various embodiments of the invention, the package 167 may comprise one or more layers and/or areas of ferromagnetic and/or ferrimagnetic material. The chip 162 may be coupled to the package 167, and the package 167 to a PCB (not shown), via solder balls 408. A surface mount component 452 may be mounted to the package 167, and thermal epoxy 414 may be pressed between the chip 162 and the package 167.

The chip 162 may be as described with respect to, for example, FIGS. 1-3. Additionally, the chip 162 may be bump-bonded or flip-chip bonded to the package 167 utilizing solder balls (e.g. solder balls 408). In this manner, wire bonds connecting the chip 162 to the package 167 may be eliminated, reducing and/or eliminating uncontrollable stray inductances due to wire bonds. In addition, the thermal conductance out of the chip 162 may be greatly improved utilizing the solder balls 408 and the thermal epoxy 214. The thermal epoxy 414 may be electrically insulating but thermally conductive to allow for thermal energy to be conducted out of the chip 162 to the much larger thermal mass of the package 167.

The solder balls 408 may comprise spherical balls of metal to provide electrical, thermal and physical contact between the chip 162 and the package 167. In making the contact with the solder balls 408, the chip 162 may be pressed with enough force to squash the metal spheres somewhat, and may be performed at an elevated temperature to provide suitable electrical resistance and physical bond strength. The solder balls 408 may also be utilized to provide electrical, thermal and physical contact between the package 167 and a printed circuit board comprising other parts of, for example, the wireless device 150 described with respect to, for example, FIG. 1.

The surface mount device 452 may comprise discrete circuit elements such as resistors, capacitors, inductors, and diodes, for example. The surface mount device 452 may be soldered to the package 167 to provide electrical contact. In various embodiments of the invention, additional surface mount elements or no surface mount elements may be coupled to the package 167.

The metal layer 412 may enable the electrical connection to the plurality of taps or ports on the multi-tap T-Line 303, and the vias 410A and 410B, which may each comprise a plurality of vias, may enable electrical coupling of the multi-tap T-Line 303 to the chip 162.

In an exemplary embodiment of the invention, the vias 410A and 410B may comprise metal and/or other conductive material(s) which may communicatively couple the multi-tap T-Line 303 to the solder balls 408. In this manner, signals may be conveyed to and/or from the chip 162 and the multi-tap T-Line 303.

In operation, the chip 162 and associated package 167 may be utilized to transmit and/or receive RF signals. The chip 162 may be electrically coupled to the multi-tap T-Line 303 embedded on and/or integrated within the package 167. In this manner, signals may be filtered utilizing configurable MOS capacitors, such as the MOS transistors 201A and 201B, and the matching circuitry module 165, described with respect to FIGS. 1-3. A resonance frequency configured by the matching circuitry module 165 may enable MOS transistor pairs to act as a variable capacitor for signals at the resonance frequency, and a shunt to ground for signals not at the resonant frequency, thereby enabling a tunable high-frequency filter on the chip 162 and/or the package 167.

In various embodiments of the invention, additional devices, for example, capacitors, inductors, and/or resistors, may be integrated into the package 167 without deviating from the scope of the present invention.

FIG. 5 is a block diagram illustrating exemplary steps for utilizing a variable MOS capacitor, in accordance with an embodiment of the invention. Referring to FIG. 5, in step 503 after start step 501, the desired frequency for received signals may be determined. In step 505, the variable inductance and capacitance may be configured for a resonance frequency of the matching circuit module at that desired frequency, followed by step 507, where the MOS capacitor may be biased and the received signals may be filtered. If, in step 509, the wireless device 150 is to be powered down, the exemplary steps may proceed to end step 511, but if not the exemplary steps may proceed back to step 503.

In an embodiment of the invention, a method and system are disclosed for filtering undesired signals in a chip utilizing one or more configurable MOS capacitors 164 comprising one or more MOS transistors 201A and 201B. The source and drain terminals of the MOS transistors 201A and 201B may be coupled together. The filtering frequencies may be tuned by configuring a resonance frequency of a matching circuit 165 coupled to the source and drain terminals. The matching circuit 165 may comprise a variable capacitor 203, which may comprise an array of binary-weighted addressable capacitors. The addressable capacitors may comprise MOS transistors. The matching circuit 165 may comprise a variable inductor 205 such as a multi-tap transmission line 303, and may be integrated on the chip 162 and/or on a package 167 to which the chip 162 is bonded. A capacitance value of the configurable MOS capacitor 164 may be configured utilizing a bias voltage V_(B) on the matching circuit 165.

Another embodiment of the invention may provide a machine and/or computer readable storage and/or medium, having stored thereon, a machine code and/or a computer program having at least one code section executable by a machine and/or a computer, thereby causing the machine and/or computer to perform the steps as described herein for a configurable tuned MOS capacitor.

Accordingly, aspects of the invention may be realized in hardware, software, firmware or a combination thereof. The invention may be realized in a centralized fashion in at least one computer system or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware, software and firmware may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.

One embodiment of the present invention may be implemented as a board level product, as a single chip, application specific integrated circuit (ASIC), or with varying levels integrated on a single chip with other portions of the system as separate components. The degree of integration of the system will primarily be determined by speed and cost considerations. Because of the sophisticated nature of modern processors, it is possible to utilize a commercially available processor, which may be implemented external to an ASIC implementation of the present system. Alternatively, if the processor is available as an ASIC core or logic block, then the commercially available processor may be implemented as part of an ASIC device with various functions implemented as firmware.

The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context may mean, for example, any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form. However, other meanings of computer program within the understanding of those skilled in the art are also contemplated by the present invention.

While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims. 

1. A method for enabling wireless communication, the method comprising: in a chip comprising a plurality of transmitters, a plurality of receivers, a matching circuit, and one or more pairs of configurable MOS capacitors comprising one or more pairs of MOS transistors, integrated on a single substrate, performing functions comprising: filtering undesired signals from an input signal applied across gate terminals of each of said one or more pairs of MOS transistors, wherein source and drain terminals of each of said one or more pairs of MOS transistors are coupled together at an output terminal; and configuring a resonance frequency of said matching circuit coupled to said source and drain terminals to enable said filtering of said undesired signals.
 2. The method according to claim 1, wherein said matching circuit comprises a variable capacitor, and said functions comprising configuring a capacitance value of said variable capacitor.
 3. The method according to claim 2, wherein said matching circuit comprises a variable capacitor, and said functions comprising configuring said variable capacitor utilizing an array of addressable capacitors.
 4. The method according to claim 3, wherein said matching circuit comprises a variable capacitor, and said functions comprising configuring said variable capacitor utilizing an array of binary-weighted addressable capacitors.
 5. The method according to claim 3, wherein said matching circuit comprises a variable capacitor, and said functions comprising configuring said variable capacitor utilizing MOS transistors as addressable capacitors.
 6. The method according to claim 1, wherein said matching circuit comprises a variable inductor, and said functions comprising configuring an inductance value of said variable inductor.
 7. The method according to claim 6, wherein said matching circuit comprises a variable inductor, and said functions comprising configuring said variable inductor utilizing a multi-tap transmission line.
 8. The method according to claim 7, wherein said matching circuit comprises a variable inductor, and said functions comprising configuring said variable inductance utilizing said multi-tap transmission line integrated on said chip.
 9. The method according to claim 7, wherein said matching circuit comprises a variable inductor, and said functions comprising configuring said variable inductance utilizing said multi-tap transmission line integrated on a package to which said chip is bonded.
 10. The method according to claim 1, said functions comprising configuring a capacitance value of said configurable MOS capacitor utilizing a bias voltage on said matching circuit.
 11. A system for enabling communication, the system comprising: one or more circuits integrated on a single substrate of a chip, said one or more circuits comprising a plurality of transmitters, a plurality of receivers, and one or more pairs of configurable MOS capacitors comprising one or more pairs of MOS transistors, wherein said one or more circuits are operable to: filter undesired signals from an input signal applied across gate terminals of each of said one or more pairs of MOS transistors, wherein source and drain terminals of each of said one or more pairs of MOS transistors are coupled together at an output terminal; and configure a resonance frequency of a matching circuit coupled to said source and drain terminals to enable said filtering of said undesired signals.
 12. The system according to claim 11, wherein said matching circuit comprises a variable capacitor.
 13. The system according to claim 12, wherein said variable capacitor comprises an array of addressable capacitors.
 14. The system according to claim 13, wherein capacitances of said addressable capacitors are binary-weighted.
 15. The system according to claim 13, wherein said addressable capacitors comprise MOS transistors.
 16. The system according to claim 11, wherein said matching circuit comprises a variable inductor.
 17. The system according to claim 16, wherein said variable inductor comprises a multi-tap transmission line.
 18. The system according to claim 17, wherein said multi-tap transmission line is integrated on said chip.
 19. The system according to claim 17, wherein said multi-tap transmission line is integrated on a package to which said chip is bonded.
 20. The system according to claim 11, wherein said one or more circuits are operable to configure a capacitance value of said configurable MOS capacitor utilizing a bias voltage on said matching circuit. 